My take on the Gartner Hype Cycle | by Jens Møllerhøj | Medium
EETimes - Eta's Ultra Low-Power Machine Learning Platform
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
AI 2.0 - Episode #1, Introduction | Cisco Tech Blog
DARPA asks industry for SWaP-optimized machine learning real-time ASICs able to learn from data | Military Aerospace
Machine Learning in Energy - ADG Efficiency
FPGA Based Deep Learning Accelerators Take on ASICs
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
Google AI Blog: Chip Design with Deep Reinforcement Learning
Are ASIC Chips The Future of AI?
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
Arch-Net: A Family Of Neural Networks Built With Operators To Bridge The Gap Between Computer Architecture of ASIC Chips And Neural Network Model Architectures - MarkTechPost
Why ASICs Are Becoming So Widely Popular For AI
Intel Speeds AI Development, Deployment and Performance with New Class of AI Hardware from Cloud to Edge | Business Wire
Easing the Effort: Mipsology Accelerates ML with Zebra FPGA IP - News
FPGA Based Deep Learning Accelerators Take on ASICs
Deep Learning Has Hit a Wall, Intel's Rao Says
ASIC Design Services | Microsemi
Being Intelligent about AI ASICs - SemiWiki
The New Deep Learning Memory Architectures You Should Know About — eSilicon Technical Article | ChipEstimate.com
Deep Neural Network ASICs The Ultimate Step-By-Step Guide: Blokdyk, Gerardus: 9780655403975: Amazon.com: Books
The Definitive Guide to Deep Learning with GPUs | cnvrg.io
My take on the Gartner Hype Cycle | by Jens Møllerhøj | Medium
FPGA chips are coming on fast in the race to accelerate AI | VentureBeat
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
